1. Field of the Invention
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package and a fabrication method thereof for improving the product yield.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIGS. 1A to 1C are schematic cross-sectional views showing a method for fabricating a semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a silicon substrate 10′ is provided and a plurality of through holes 100a are formed in the silicon substrate 10′.
Referring to FIG. 1B, a dielectric material 100b is formed in the through holes 100a first and then a metal material is filled in the through holes 100a, thus forming a silicon interposer 10 having a plurality of through silicon vias (TSVs) 100.
Referring to FIG. 1C, an RDL (Redistribution Layer) structure 15 is formed on a first surface of the silicon interposer 10.
Then, a semiconductor chip 11 having a plurality of electrode pads 110 is flip-chip disposed on a second surface of the silicon interposer 10 opposite to the first surface. The electrode pads 110 are electrically connected to the TSVs 100 of the silicon interposer 10 through a plurality of u-bumps 13. Thereafter, an underfill 12 is formed between the semiconductor chip 11 and the silicon interposer 10 for encapsulating the u-bumps 13.
Then, an encapsulant 16 is formed on the silicon interposer 10 for encapsulating the semiconductor chip 11.
Thereafter, a packaging substrate 18 having a plurality of bonding pads 180 is attached to the first surface of the silicon interposer 10 through the RDL structure 15. In particular, the RDL structure 15 is electrically connected to the bonding pads 180 through a plurality of conductive elements 17 having a large pitch. Further, an underfill 12 is formed between the RDL structure 15 and the packaging substrate 18 for encapsulating the conductive elements 17.
If the semiconductor chip 11 is directly attached to the packaging substrate 18, a big CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chip 11 and the packaging substrate 18 adversely affects the formation of joints between conductive bumps of the semiconductor chip 11 and the bonding pads 180 of the packaging substrate 18, thus easily resulting in delamination of the conductive bumps from the packaging substrate 18. On the other hand, the CTE mismatch between the semiconductor chip 11 and the packaging substrate 18 induces more thermal stresses and leads to more serious warpage, thereby reducing the reliability of electrically connection between the semiconductor chip 11 and the packaging substrate 18 and resulting in failure of a reliability test.
Therefore, the silicon interposer 10 close in material to the semiconductor chip 11 is disposed between the semiconductor chip 11 and the packaging substrate 18 so as to effectively overcome the above-described drawbacks.
Further, the silicon interposer 10 facilitates to reduce the area of the semiconductor package 1. For example, a packaging substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the packaging substrate cannot be reduced, the area of the packaging substrate must be increased such that more circuits can be formed on the packaging substrate and electrically connected to the semiconductor chip. On the other hand, referring to FIG. 1, through a semiconductor process, the silicon interposer 10 can have a line width/pitch of 3/3 um or less. Therefore, the semiconductor chip 11 having a high I/O count can be disposed on the silicon interposer 10 without the need to increase the area of the packaging substrate 18.
However, to form the TSVs 100 of the silicon interposer 10, a plurality of through holes 100a need to be formed in the silicon substrate 10′ through a patterning process such as exposure, development and etching and then filled with metal, which incurs a high cost. For example, for a 12-inch wafer, the TSV cost occupies about 40 to 50% of the total cost for fabricating the silicon interposer 10 (not including labor cost). Further, the fabrication process of the TSVs is time-consuming, especially when the silicon substrate 10′ is etched to form the through holes 100a. Consequently, the cost of the final product is increased.
Therefore, how to overcome the above-described drawbacks has become critical.